Flash : Write Amplification, Bit Error Rate & ECC Algorithms

Just like any new technology, along with the “wow” factor comes the limitations, “flash storage” in its native state also has issues which need to be dealt by every vendor to make it more reliable, provide better endurance and thus increase the life of a flash chip. I am hereby using this blog post as a center-stage to discuss the concerns and the methods which every vendor accustoms to increase the longevity of their flash chip.

Write Amplification

“Write Amplification”, as the name implies, is a phenomenon which increase the number of “writes’, where the actual amount of physical information written is a multiple of the logical amount intended to be written. It plays a critical role in increasing the endurance of a flash chip.

The lower the write amplification, the longer the flash will last.  Flash architects pay special attention to this aspect of controller design.Picture22

From what I explained so far, many operations like garbage collection, wear leveling, etc. keep happening at the background and the process to perform these operations results in moving (or rewriting) user data and metadata more than once.

Thus, rewriting some (one cell) data requires an already used portion of flash to be read, updated and written to a new location, together with initially erasing the new location if it was previously used at some point in time; due to the way flash works, much larger portions of flash must be erased and rewritten than actually required by the amount of new data.

This multiplying effect increases the number of “writes” required over the life of the flash which shortens the time it can reliably operate.

Vendors use various techniques like compression, deduplication (it has other implications where garbage collection algorithm or wear leveling algorithm has to communicate with hash algorithm to do the erase, thus increasing the load on processor) etc. to drop the write amplification and increase the life span of the chip.

Bit – Error Rate

Bit error rate as the definition says, is the number of “bit” errors occured in a particular interval of time. Errors can occur because of a number of reasons. There are two main reasons because of which “bit” errors occur.

  • Read / Write disturb
  • Charge getting trapped

Program (or write) or Read Disturb – Due to small size of flash gates in MLC, when you apply threshold voltage (as explained in “Understanding flash at its core”) to read or program a cell there is every chance the cells nearby (within the same block) might get disturbed because of which their program state might change or get slightly programmed which otherwise would get nullified when an erase operation happens or error correction code (ECC) algorithms are used to correct the same.

Picture23Charge Getting TrappedWhen you are programming a cell or erasing a cell there is chance that electrons might get trapped in the tunnel oxide layer between the floating gate and the semiconductor while tunneling. This usually happens when cells have been programmed and erased quite a few times and tunnel oxide layer has become weak. Advanced error correction code algorithms are stored alongside user data to ensure that incorrect information is spotted and dealt with while any underlying pages are marked as unusable.

NAND Flash errors can also be caused by elevated heat, manufacturing defects, or even simply repeated use, also known as wear out. Hence, the error correction code (ECC) algorithms used and at what level the vendor has programmed to handle these errors becomes important while measuring the endurance of a flash system.

Error Correction Code (ECC) Algorithms

Error correction code algorithms have a big impact on the endurance of a flash chip.Picture18

All NAND flash requires ECC to correct random “bit” errors. In an attempt to make NAND flash cheap, the voltage passed through the NAND flash has become very narrow because of which the errors like read disturb, program disturb, errors due to wear, etc. occur.

Error correction code algorithm also has two types of code,

  1. Predictable errors check, which helps to correct errors that are caused by internal mechanisms that are inherent to the design of the chip.  A prime example of such an error would be adjacent cell disturb.
  2. Unpredictable errors check, which help in correcting more unpredictable wear that occurs due to charge getting trapped, elevated heat, etc. which are not expected to happen due to measures already in place. In short this algorithm handles more complex errors.

More sophisticated ECC requires more processing power in the controller and may be slower than less sophisticated algorithms.  Also, the number of errors that can be corrected can depend upon how large a segment of memory is being corrected.  A controller with elaborate ECC capabilities is likely to use more compute resources and more internal RAM than would one with simpler ECC.  These enhancements will make the controller more expensive hence the increase in cost of a flash device.

Another thing, I did not mention is the math behind the error correction code algorithm. I am mesmerized by the aptitude of the folks who have mastered ECC, and their ability to extract more life out of a flash block than any mere mortal would think possible. I am not attempting to explain the same in this blog as I want this blog to be simple for anyone to understand.

Last but not the least, every error correction code algorithm is designed to correct only a limited (this usually depends on research that an organization has done on the flash chip) number of errors which actually determines the lifespan of a flash chip.

References: SAN Disk, Toshiba, Micron, IBM Redbooks


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