Understanding flash chip at its core

When I started researching about flash, I delved into flash technology so deep that I felt it would be difficult for my reader to understand the SLC, MLC, eMLC, etc. of flash technology without explaining the base of flash chip construction, and the physics behind it. Hence I have decided to write a bit on the basics first, and then jump into much-detailed intended topics.

Flash Architecture

Flash is a type of non-volatile, solid-state storage technology. In enterprise applications, multiple Flash chips are used together to produce modules in the form of external rack mount systems or internal cards or drives.

A Flash memory chip is divided into multiple nested entities as below.

Picture5

  • The flash chip is the black box or rectangle you would see in every picture online. If you look at an SSD, a flash card or the internals of a flash array you will see many flash chips, each of whicPicture4h is produced by one of the big flash manufacturers like Toshiba, Samsung, Micron, Intel, SanDisk, etc.
  • Each flash chip contains eight dies. The die is the smallest unit that can independently execute commands or report status.
  • Each die contains two planes. Identical, concurrent operations can take place on each plane although with some restrictions.
  • Each plane contains 2048 blocks, which are the smallest unit that can be erased.
  • Each block contains 64 pages, which are the smallest unit that can be programmed (i.e. written to) and this is where error correction code algorithms are applied. A page is a collection of cells (which I would be talking about while explaining how flash works)

The write operations that take place to a page, are typically 8-16KB in size while erase operations take place to a block, are 4-8MB in size.

How does a flash chip function?

This is a bit complicated for those who are from a non-physics background. I shall simplify and explain it’s working in layman terms.

Picture2

In the picture above imagine source as the starting point of the flow of electrons and drain is the destination. Control Gate is where the charge is applied to make the semiconductor move the electrons from source to drain. You will see in the picture above that there is an insulator, which is nothing but the oxide layer which prevents the control gate from directly attaching to the source or drain. This way of working of a transistor is called MOSFET (Metal Oxide Semiconductor Field Effect Transistor).

In case of a flash cell what you find is FGMOSFET (Floating Gate Metal Oxide Semiconductor Field Effect Transistor)

Picture3

If you compare both the pictures above, you would see an additional gate called floating gate (as it is completely separated) in the picture of a flash cell which is between the control gate and the conductor. You will also notice an additional oxide layer called tunnel oxide layer which is thinner than the blocking oxide layer.

How the floating gate functions is what tells us how a flash cell works? When you apply high charge at control gate electrons flowing from source to drain will tunnel or jump (this is called tunneling) through the tunnel oxide layer to floating gate and thus retaining the charge there, this is called programming state of the flash cell.

To erase the charge stored on the floating gate a high voltage is applied from source to drain and a negative voltage is applied to the control gate which makes the electrons stored on the floating gate to tunnel or move back their original path.

With the electrons in the floating gate in a program state, control gate has to apply a higher charge to make the semiconductor conduct the cells.

After understanding how a programming/write operation & erase operation happens it is also important for us to understand how a read operation happens.

For a reading operation a voltage (VT) which is intermediate between the threshold voltages of program state (VT0) and a voltage (VT1) which the control gPicture1ate applies to make the semiconductor conduct is applied. If there are no electrons in the floating gate it would make the semiconductor to conduct and thus return a logical value “1” but if there are electrons present in the floating gate it does not conduct and returns a logical value “0”. This again varies in different cells (SLC, MLC, etc.), which I will explain in further posts.

Having explained all this complicated story of how a flash chip works there are few points I want you to remember which actually would form the basis of my further posts as I explain the difference between various cells and how they are used.

  • In an FGMOSFET the tunnel oxide layer which isolates the floating gate from the semiconductor is designed to be thin enough to allow tunneling of electrons when a high enough charge is applied, but this process gradually damages the layer.
  • Reads are not a problem because only lower voltages are used and no electron tunneling takes place.
  • In the case of program and erase operations it’s a different story, which is why wear is measured by the number of program/erase cycles.
  • As the layer gets more damaged, the isolation of the floating gate is increasingly affected and the probability of electrons leaking out will increase.

To conclude, in this article I have tried to explain how the flash chip works in the most simplest of means. Having covered the basics, the next chapter will embark on explaining the different cells, and how their design is modified to achieve significant purposes (and operations).

References : Micron; SAN Disk

 

Advertisements